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Do my kkr capstone insead

Do my kkr capstone insead write for me capstone grand canyon university syllabus essay word count quotes about beauty ´╗┐hello my name is Sriram rajagopal and I'm an application engineer at EMA design automation I have created this small utility which will convert your VHDL files to use it along with pspice and this video is going to show you how you lot follow a set of instructions or steps to achieve this goal first extract your files under C colon program files next you'll have to synthesize your RTL VHDL and generate a gate level VHDL file you'll have to say if this gate level VHDL file in a predefined directory I will show you in this movie next you will have to use the program that I have created and converted into a pspice notation and then from there onwards you will create a schematic symbol and use it along with your analog or mixed signal components in your pspice project you should also be aware of something here that the utility that I have created is not something that EMA or cadence actively supports ourselves so this is purely something that I have created to help other pspice users so I have not benchmarked the function or performance of this utility so you love use it and understand that you're using it at your own risk so let me proceed ahead and show you how to use this utility first you will have to extract the contents of the compressed folder that I have emailed you this you'll have to extract it under C colon program files now this is very important because it has to be in this location for the utility to to read and write so let's extract it here under C colon program files this will create a folder called VHDL to pspice now let's look at the contents of this folder it has several subfolders and you will know why all these folders are there as you proceed along as the name indicates the first one is where you save all the captured schematic symbols the library folder is a folder where all the piecewise digital models are created this is something that you would keep on adding after you use the utility and there is also a folder called Delphi examples where I have kept all the sample exam sample files for our Karen VHDL files that I'll be using in this example and there is also a source folder where I would use to save all my gate level VHDL files now let's go to start programs and bring up the lattice and simplify software to synthesize your gate level VHDL file you don't have to be a proficient simplified user to use this utility and I will show you how go to file new and create a new project then you need to add your VHDL RTL VHDL file so right click and say add source and in this example I've also kept your VHDL file under Delphi examples the file name is called one dot VHD this is a simple counter now what I assume here is that this counter has been already verified and it's ready for synthesis so you'll have to code your VHDL accordingly you also need to setup certain conditions before synthesis so select this folder right click and bring up the implementation options so you need to synthesize using the lattice mac-11 one technology and disable IO insertions go to the implementation tab and check the VHDL netlist checkbox now you are ready is ready to synthesize hit the Run button and this will generate a bunch of output files we are interested in the gate level VHDL file so this is this has an extension dot V hm let's double click on this file to look at what it looks like this is a typical gate level VHDL file that is generated by the synthesis tool so we need this file so we need to go to file save as and we need to save it under C colon program files VHDL to pspice and under the source directory once the file is saved we are pretty much done with synthesis so we can close simplicity so let's go back and run the utility that I have created which will convert the gate level VHDL file to its equivalent pspice notation the utility is called VHDL to pspice underscore Shriram so first you need to enter the name of your VHDL gate level VHDL file so it's called one there is no need to enter the extension click OK next you need to enter the name of your top-level entity in this case it is called counter so hit OK and it is all almost immediately it converts it into its equivalent pspice representation now let's look at the output files that this is created let's go into the library file folder you can see that there are a bunch of files that already exist the one that was recently created was the copy 1 dot ALAB every time you run the utility it will create a dot Li B file and the way Mike program works is that it prefixes prefix a word called copy in front of the output files it also has Creek it has created another folder another file called lip pointer dot Li B now let me open this in notepad and this is a library pointer file so this file will tell pspice where to look for the libraries when it's running simulation so we just created the li b file now we need to create an equivalent schematic representation so we need to go to OrCAD capture I'm sorry our cat 10.5 pspice accessories model editor and open the Li B file that was created using the software as you can see this represents the structural or the gate level VHDL file in its equivalent pspice notation basically a subcircuit file now you need to go to file export to capture library and choose an appropriate destination path now you should go to your folder VHDL to pspice where there is a subfolder called captured capture symbols this is typically where you need to keep all your olb files when you run this utility now I'm also going to show you an orc at capture pspice project where you're going to use this symbol that we just created there is I've already created an example so this example is under your Program Files VHDL to pspice delphi examples and name of the example is called counter underscore VHDL let's bring up the project what I've done here is I've already placed the symbol all you have to do is go to the place part option and browse to the location of to your olb file which is under capture symbols directory so choose that and click open and then place the symbol I have also connected inputs to my clock and reset so these are the inputs are coming from a digital stimulus these stimulus are from the capture sorry pspice stimulus library now let's look at these stimulus to see what its behavior is like so this is has a period hundred nanoseconds with a repetition of 50 nanoseconds once again these are within your default piecewise libraries it's from the source s TM and the part is called ditch stem one these are very easy to use next what you have to do is you'll have to edit your simulation settings go to edit simulation settings and click on the configuration tabs and choose the library category browse to the folder within the VHDL to pspice directory go to the library folder and choose the lip pointer dot Li B as I said earlier this file will point or help piecewise understand where all your custom created models are saved within your computer so you can either add to design or address global either either way it's fine and click OK just to make sure that everything is connected correctly you can check selecting the symbol right click and then say edit pspice model and immediately you should be able to see the model definition which is nothing but B which is nothing but the reach VHDL gate level representation in pspice so let's run simulations I have added my inputs and outputs in this example by clicking on add trace button as I said this is a counter which will count all the clock pulses this is an ideal example so there are no delays so this is how you would use and connect it with other components in your design thank you for your time write for me capstone pharmacy school Hilbert College, Hamburg.

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